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<div class="header">
  <div class="summary">
<a href="#groups">API Reference</a>  </div>
  <div class="headertitle">
<div class="title">SPI (SCB)<div class="ingroups"><a class="el" href="group__group__scb.html">SCB          (Serial Communication Block)</a></div></div>  </div>
</div><!--header-->
<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
<p>Driver API for SPI Peripheral. </p>
<p>The functions and other declarations used in this part of the driver are in cy_scb_spi.h. You can also include cy_pdl.h to get access to all functions and declarations in the PDL.</p>
<p>The SPI protocol is a synchronous serial interface protocol. Devices operate in either master or slave mode. The master initiates the data transfer. The SCB supports single-master-multiple-slaves topology for SPI. Multiple slaves are supported with individual slave select lines.</p>
<p>Features:</p><ul>
<li>Supports master and slave functionalitySupports three types of SPI protocols:<ul>
<li>Motorola SPI - modes 0, 1, 2, and 3</li>
<li>Texas Instruments SPI, with coinciding and preceding data frame indicator - mode 1 only</li>
<li>National Semiconductor (MicroWire) SPI - mode 0 only</li>
</ul>
</li>
<li>Master supports up to four slave select lines<ul>
<li>Each slave select has configurable active polarity (high or low)</li>
<li>Slave select can be programmed to stay active for a whole transfer, or just for each byte</li>
</ul>
</li>
<li>Master supports late sampling for better timing margin</li>
<li>Master supports continuous SPI clock</li>
<li>Data frame size programmable from 4 bits to 32 bits</li>
<li>Programmable oversampling</li>
<li>MSb or LSb first</li>
<li>Median filter available for inputs</li>
</ul>
<h1><a class="anchor" id="group_scb_spi_configuration"></a>
Configuration Considerations</h1>
<p>The SPI driver configuration can be divided to number of sequential steps listed below:</p><ul>
<li><a class="el" href="group__group__scb__spi.html#group_scb_spi_config">Configure SPI</a></li>
<li><a class="el" href="group__group__scb__spi.html#group_scb_spi_pins">Assign and Configure Pins</a></li>
<li><a class="el" href="group__group__scb__spi.html#group_scb_spi_clock">Assign Clock Divider</a></li>
<li><a class="el" href="group__group__scb__spi.html#group_scb_spi_data_rate">Configure Data Rate</a></li>
<li><a class="el" href="group__group__scb__spi.html#group_scb_spi_intr">Configure Interrupt</a></li>
<li><a class="el" href="group__group__scb__spi.html#group_scb_spi_enable">Enable SPI</a></li>
</ul>
<dl class="section note"><dt>Note</dt><dd>The SPI driver is built on top of the SCB hardware block. The SCB1 instance is used as an example for all code snippets. Modify the code to match your design.</dd></dl>
<h2><a class="anchor" id="group_scb_spi_config"></a>
Configure SPI</h2>
<p>To set up the SPI driver, provide the configuration parameters in the <a class="el" href="structcy__stc__scb__spi__config__t.html">cy_stc_scb_spi_config_t</a> structure. For example: provide spiMode, subMode, sclkMode, oversample, rxDataWidth, and txDataWidth. The other parameters are optional for operation. To initialize the driver, call <a class="el" href="group__group__scb__spi__general__functions.html#gabe68169c810119b93e1164127663033c">Cy_SCB_SPI_Init</a> function providing a pointer to the populated <a class="el" href="structcy__stc__scb__spi__config__t.html">cy_stc_scb_spi_config_t</a> structure and the allocated <a class="el" href="structcy__stc__scb__spi__context__t.html">cy_stc_scb_spi_context_t</a> structure.</p>
<div class="fragment"><div class="line"><span class="comment">/* Allocate context for SPI operation */</span></div><div class="line"><a class="code" href="structcy__stc__scb__spi__context__t.html">cy_stc_scb_spi_context_t</a> spiContext;</div><div class="line"></div><div class="line"><span class="comment">/* Populate configuration structure */</span></div><div class="line"><span class="preprocessor">#if (USE_SPI_SLAVE)</span></div><div class="line">    <span class="comment">/* Slave configuration */</span></div><div class="line">    <a class="code" href="structcy__stc__scb__spi__config__t.html">cy_stc_scb_spi_config_t</a> spiConfig =</div><div class="line">    {</div><div class="line">        .<a class="code" href="structcy__stc__scb__spi__config__t.html#a4fc24e3daa02dc8a81de14341a954110">spiMode</a>  = <a class="code" href="group__group__scb__spi__enums.html#gga931ca8a003e3da524aadd562945d3ab5a6b016365095f773e900be90867db0976">CY_SCB_SPI_SLAVE</a>,</div><div class="line">        .subMode  = <a class="code" href="group__group__scb__spi__enums.html#gga1410916a9c76b0d86eb196b8e9ed547fa62fab87ba422296db9c490c3b74830ab">CY_SCB_SPI_MOTOROLA</a>,</div><div class="line">        .sclkMode = <a class="code" href="group__group__scb__spi__enums.html#ggab34eae51343cebfec7c447a573cdf0baac7839625f0402b7b9685f3fc2c8a2305">CY_SCB_SPI_CPHA0_CPOL0</a>,</div><div class="line">        .oversample = 0UL, </div><div class="line"></div><div class="line">        .rxDataWidth              = 8UL,</div><div class="line">        .txDataWidth              = 8UL,</div><div class="line">        .enableMsbFirst           = <span class="keyword">false</span>,</div><div class="line">        .enableInputFilter        = <span class="keyword">false</span>,</div><div class="line">        .enableFreeRunSclk        = <span class="keyword">false</span>,</div><div class="line">        .enableMisoLateSample     = <span class="keyword">false</span>,</div><div class="line">        .enableTransferSeperation = <span class="keyword">false</span>,</div><div class="line">        .ssPolarity               = <a class="code" href="group__group__scb__spi__enums.html#ggac1d52a37938101b62b908fb4263d98a2ab36d0ae32e47bb37ec614d9bc58b7198">CY_SCB_SPI_ACTIVE_LOW</a>,</div><div class="line">        .enableWakeFromSleep      = <span class="keyword">false</span>,</div><div class="line"></div><div class="line">        .rxFifoTriggerLevel  = 0UL,</div><div class="line">        .rxFifoIntEnableMask = 0UL,</div><div class="line">        .txFifoTriggerLevel  = 0UL,</div><div class="line">        .txFifoIntEnableMask = 0UL,</div><div class="line">        .masterSlaveIntEnableMask = 0UL,</div><div class="line">    };</div><div class="line"><span class="preprocessor">#else</span></div><div class="line">    <span class="comment">/* Master configuration */</span></div><div class="line">    <a class="code" href="structcy__stc__scb__spi__config__t.html">cy_stc_scb_spi_config_t</a> spiConfig =</div><div class="line">    {</div><div class="line">        .<a class="code" href="structcy__stc__scb__spi__config__t.html#a4fc24e3daa02dc8a81de14341a954110">spiMode</a>  = <a class="code" href="group__group__scb__spi__enums.html#gga931ca8a003e3da524aadd562945d3ab5aac0d1cba1a96754415d7457a35cf6510">CY_SCB_SPI_MASTER</a>,</div><div class="line">        .subMode  = <a class="code" href="group__group__scb__spi__enums.html#gga1410916a9c76b0d86eb196b8e9ed547fa62fab87ba422296db9c490c3b74830ab">CY_SCB_SPI_MOTOROLA</a>,</div><div class="line">        .sclkMode = <a class="code" href="group__group__scb__spi__enums.html#ggab34eae51343cebfec7c447a573cdf0baac7839625f0402b7b9685f3fc2c8a2305">CY_SCB_SPI_CPHA0_CPOL0</a>,</div><div class="line">        .oversample = 10UL,</div><div class="line"></div><div class="line">        .rxDataWidth              = 8UL,</div><div class="line">        .txDataWidth              = 8UL,</div><div class="line">        .enableMsbFirst           = <span class="keyword">false</span>,</div><div class="line">        .enableInputFilter        = <span class="keyword">false</span>,</div><div class="line">        .enableFreeRunSclk        = <span class="keyword">false</span>,</div><div class="line">        .enableMisoLateSample     = <span class="keyword">true</span>,</div><div class="line">        .enableTransferSeperation = <span class="keyword">false</span>,</div><div class="line">        .ssPolarity               = <a class="code" href="group__group__scb__spi__enums.html#ggac1d52a37938101b62b908fb4263d98a2ab36d0ae32e47bb37ec614d9bc58b7198">CY_SCB_SPI_ACTIVE_LOW</a>,</div><div class="line">        .enableWakeFromSleep      = <span class="keyword">false</span>,</div><div class="line"></div><div class="line">        .rxFifoTriggerLevel  = 0UL,</div><div class="line">        .rxFifoIntEnableMask = 0UL,</div><div class="line">        .txFifoTriggerLevel  = 0UL,</div><div class="line">        .txFifoIntEnableMask = 0UL,</div><div class="line">        .masterSlaveIntEnableMask = 0UL,</div><div class="line">    };</div><div class="line"><span class="preprocessor">#endif</span></div><div class="line"></div><div class="line"><span class="comment">/* Configure SPI to operate */</span></div><div class="line">(void) <a class="code" href="group__group__scb__spi__general__functions.html#gabe68169c810119b93e1164127663033c">Cy_SCB_SPI_Init</a>(SCB1, &amp;spiConfig, &amp;spiContext);</div></div><!-- fragment --><h2><a class="anchor" id="group_scb_spi_pins"></a>
Assign and Configure Pins</h2>
<p>Only dedicated SCB pins can be used for SPI operation. The HSIOM register must be configured to connect dedicated SCB SPI pins to the SCB block. Also, the SPI output pins must be configured in Strong Drive Input Off mode and SPI input pins in Digital High-Z.</p>
<div class="fragment"><div class="line"><span class="comment">/* Assign pins for SPI on SCB1: P10[0], P10[1], P10[2] and P10[3] */</span></div><div class="line"><span class="preprocessor">#define SPI_PORT        P10_0_PORT</span></div><div class="line"><span class="preprocessor">#define SPI_MISO_NUM    P10_0_NUM</span></div><div class="line"><span class="preprocessor">#define SPI_MOSI_NUM    P10_1_NUM</span></div><div class="line"><span class="preprocessor">#define SPI_SCLK_NUM    P10_2_NUM</span></div><div class="line"><span class="preprocessor">#define SPI_SS_NUM      P10_3_NUM</span></div><div class="line"></div><div class="line"><span class="comment">/* Connect SCB1 SPI function to pins */</span></div><div class="line"><a class="code" href="group__group__gpio__functions__init.html#ga83a06264feed0e1042671a74339ea155">Cy_GPIO_SetHSIOM</a>(SPI_PORT, SPI_MISO_NUM, P10_1_SCB1_SPI_MISO);</div><div class="line"><a class="code" href="group__group__gpio__functions__init.html#ga83a06264feed0e1042671a74339ea155">Cy_GPIO_SetHSIOM</a>(SPI_PORT, SPI_MOSI_NUM, P10_0_SCB1_SPI_MOSI);</div><div class="line"><a class="code" href="group__group__gpio__functions__init.html#ga83a06264feed0e1042671a74339ea155">Cy_GPIO_SetHSIOM</a>(SPI_PORT, SPI_SCLK_NUM, P10_2_SCB1_SPI_CLK);</div><div class="line"><a class="code" href="group__group__gpio__functions__init.html#ga83a06264feed0e1042671a74339ea155">Cy_GPIO_SetHSIOM</a>(SPI_PORT, SPI_SS_NUM,   P10_3_SCB1_SPI_SELECT0);</div><div class="line"></div><div class="line"><span class="preprocessor">#if (USE_SPI_SLAVE)</span></div><div class="line">    <span class="comment">/* Configure SCB1 pins for SPI Slave operation */</span></div><div class="line">    <a class="code" href="group__group__gpio__functions__gpio.html#ga97e64dc8c45e7cd73e3012100d03b1fd">Cy_GPIO_SetDrivemode</a>(SPI_PORT, SPI_MISO_NUM, <a class="code" href="group__group__gpio__drive_modes.html#gacebd8bea6222d742bdfbfd86dabab940">CY_GPIO_DM_STRONG_IN_OFF</a>);</div><div class="line">    <a class="code" href="group__group__gpio__functions__gpio.html#ga97e64dc8c45e7cd73e3012100d03b1fd">Cy_GPIO_SetDrivemode</a>(SPI_PORT, SPI_MOSI_NUM, <a class="code" href="group__group__gpio__drive_modes.html#gaf2fe5dc00ba1770b37e620a01169485c">CY_GPIO_DM_HIGHZ</a>);</div><div class="line">    <a class="code" href="group__group__gpio__functions__gpio.html#ga97e64dc8c45e7cd73e3012100d03b1fd">Cy_GPIO_SetDrivemode</a>(SPI_PORT, SPI_SCLK_NUM, <a class="code" href="group__group__gpio__drive_modes.html#gaf2fe5dc00ba1770b37e620a01169485c">CY_GPIO_DM_HIGHZ</a>);</div><div class="line">    <a class="code" href="group__group__gpio__functions__gpio.html#ga97e64dc8c45e7cd73e3012100d03b1fd">Cy_GPIO_SetDrivemode</a>(SPI_PORT, SPI_SS_NUM,   <a class="code" href="group__group__gpio__drive_modes.html#gaf2fe5dc00ba1770b37e620a01169485c">CY_GPIO_DM_HIGHZ</a>);</div><div class="line"><span class="preprocessor">#else </span><span class="comment">/* (USE_SPI_SLAVE) */</span><span class="preprocessor"></span></div><div class="line">    <span class="comment">/* Configure SCB1 pins for SPI Master operation */</span></div><div class="line">    <a class="code" href="group__group__gpio__functions__gpio.html#ga97e64dc8c45e7cd73e3012100d03b1fd">Cy_GPIO_SetDrivemode</a>(SPI_PORT, SPI_MISO_NUM, <a class="code" href="group__group__gpio__drive_modes.html#gaf2fe5dc00ba1770b37e620a01169485c">CY_GPIO_DM_HIGHZ</a>);</div><div class="line">    <a class="code" href="group__group__gpio__functions__gpio.html#ga97e64dc8c45e7cd73e3012100d03b1fd">Cy_GPIO_SetDrivemode</a>(SPI_PORT, SPI_MOSI_NUM, <a class="code" href="group__group__gpio__drive_modes.html#gacebd8bea6222d742bdfbfd86dabab940">CY_GPIO_DM_STRONG_IN_OFF</a>);</div><div class="line">    <a class="code" href="group__group__gpio__functions__gpio.html#ga97e64dc8c45e7cd73e3012100d03b1fd">Cy_GPIO_SetDrivemode</a>(SPI_PORT, SPI_SCLK_NUM, <a class="code" href="group__group__gpio__drive_modes.html#gacebd8bea6222d742bdfbfd86dabab940">CY_GPIO_DM_STRONG_IN_OFF</a>);</div><div class="line">    <a class="code" href="group__group__gpio__functions__gpio.html#ga97e64dc8c45e7cd73e3012100d03b1fd">Cy_GPIO_SetDrivemode</a>(SPI_PORT, SPI_SS_NUM,   <a class="code" href="group__group__gpio__drive_modes.html#gacebd8bea6222d742bdfbfd86dabab940">CY_GPIO_DM_STRONG_IN_OFF</a>);</div><div class="line"><span class="preprocessor">#endif</span></div></div><!-- fragment --><h2><a class="anchor" id="group_scb_spi_clock"></a>
Assign Clock Divider</h2>
<p>A clock source must be connected to the SCB block to oversample input and output signals, in this document this clock will be referred as clk_scb. You must use one of the 8-bit or 16-bit dividers. Use the <a class="el" href="group__group__sysclk.html">SysClk (System Clock)</a> driver API to do this.</p>
<div class="fragment"><div class="line"><span class="comment">/* Assign divider type and number for SPI */</span></div><div class="line"><span class="preprocessor">#define SPI_CLK_DIV_TYPE    (CY_SYSCLK_DIV_8_BIT)</span></div><div class="line"><span class="preprocessor">#define SPI_CLK_DIV_NUMBER     (0U)</span></div><div class="line"></div><div class="line"><span class="comment">/* Connect assigned divider to be a clock source for SPI */</span></div><div class="line"><a class="code" href="group__group__sysclk__clk__peripheral__funcs.html#ga2f480c53ecec720ceed823b2692f1698">Cy_SysClk_PeriphAssignDivider</a>(PCLK_SCB1_CLOCK, SPI_CLK_DIV_TYPE, SPI_CLK_DIV_NUMBER);</div></div><!-- fragment --><h2><a class="anchor" id="group_scb_spi_data_rate"></a>
Configure Data Rate</h2>
<p>To get the SPI slave to operate with the desired data rate, the clk_scb must be fast enough to provide sufficient oversampling. Use the <a class="el" href="group__group__sysclk.html">SysClk (System Clock)</a> driver API to do that.</p>
<div class="fragment"><div class="line"><span class="comment">/* SPI data rate is defined by the SPI master because it drives SCLK.</span></div><div class="line"><span class="comment">* This clk_scb enables SPI slave operate up to maximum supported data rate.</span></div><div class="line"><span class="comment">* For clk_peri = 50 MHz, select divider value 1 and get clk_scb = (50 MHz / 1) = 50 MHz.</span></div><div class="line"><span class="comment">*/</span></div><div class="line"><a class="code" href="group__group__sysclk__clk__peripheral__funcs.html#gae7042898b1b6835673182e462be6976e">Cy_SysClk_PeriphSetDivider</a>   (SPI_CLK_DIV_TYPE, SPI_CLK_DIV_NUMBER, 0UL);</div><div class="line"><a class="code" href="group__group__sysclk__clk__peripheral__funcs.html#ga0725e2b222edc601b7d3f56d86d4ff75">Cy_SysClk_PeriphEnableDivider</a>(SPI_CLK_DIV_TYPE, SPI_CLK_DIV_NUMBER);</div></div><!-- fragment --><p> To get the SPI master to operate with the desired data rate, multiply the oversample factor by the desired data rate to determine the required frequency for clk_scb. Use the <a class="el" href="group__group__sysclk.html">SysClk (System Clock)</a> driver API to configure clk_scb frequency. Set the <em><b>oversample parameter in configuration structure</b></em> to define number of SCB clocks in one SCLK period. When this value is even, the first and second phases of the SCLK period are the same. Otherwise, the first phase is one SCB clock cycle longer than the second phase. The level of the first phase of the clock period depends on CPOL settings: 0 - low level and 1 - high level.</p>
<div class="fragment"><div class="line"><span class="comment">/* SPI master desired data rate is 1 Mbps.</span></div><div class="line"><span class="comment">* The SPI master data rate = (clk_scb / Oversample).</span></div><div class="line"><span class="comment">* For clk_peri = 50 MHz, select divider value 5 and get SCB clock = (50 MHz / 5) = 10 MHz.</span></div><div class="line"><span class="comment">* Select Oversample = 10. These setting results SPI data rate = 10 MHz / 10 = 1 Mbps.</span></div><div class="line"><span class="comment">*/</span></div><div class="line"><a class="code" href="group__group__sysclk__clk__peripheral__funcs.html#gae7042898b1b6835673182e462be6976e">Cy_SysClk_PeriphSetDivider</a>   (SPI_CLK_DIV_TYPE, SPI_CLK_DIV_NUMBER, 4UL);</div><div class="line"><a class="code" href="group__group__sysclk__clk__peripheral__funcs.html#ga0725e2b222edc601b7d3f56d86d4ff75">Cy_SysClk_PeriphEnableDivider</a>(SPI_CLK_DIV_TYPE, SPI_CLK_DIV_NUMBER);</div></div><!-- fragment --> <dl class="section note"><dt>Note</dt><dd>In CAT1D devices, to avoid potential metastable conditions at 50 MHz, set clock to 200 MHz, oversample to 4 and median filter to 1.</dd></dl>
<p><b>Refer to the technical reference manual (TRM) section SPI sub-section Oversampling and Bit Rate to get information about how to configure SPI to run with desired data rate</b>.</p>
<h2><a class="anchor" id="group_scb_spi_intr"></a>
Configure Interrupt</h2>
<p>The interrupt is optional for the SPI operation. To configure the interrupt, the <a class="el" href="group__group__scb__spi__interrupt__functions.html#ga0adeb497479d79c9ecea8169cfaff114">Cy_SCB_SPI_Interrupt</a> function must be called in the interrupt handler for the selected SCB instance. Also, this interrupt must be enabled in the NVIC. The interrupt must be configured when <a class="el" href="group__group__scb__spi.html#group_scb_spi_hl">High-Level API</a> will be used.</p>
<div class="fragment"><div class="line"><span class="keywordtype">void</span> SPI_Isr(<span class="keywordtype">void</span>)</div><div class="line">{</div><div class="line">    <a class="code" href="group__group__scb__spi__interrupt__functions.html#ga0adeb497479d79c9ecea8169cfaff114">Cy_SCB_SPI_Interrupt</a>(SCB1, &amp;spiContext);</div><div class="line">}</div></div><!-- fragment --><div class="fragment"><div class="line"><span class="keywordtype">void</span> SPI_Cfg_Isr(<span class="keywordtype">void</span>)</div><div class="line">{</div><div class="line"><span class="comment">/* Assign SPI interrupt number and priority */</span></div><div class="line"><span class="preprocessor">#define SPI_INTR_NUM        ((IRQn_Type) scb_1_interrupt_IRQn)</span></div><div class="line"><span class="preprocessor">#define SPI_INTR_PRIORITY   (7U)</span></div><div class="line"></div><div class="line"><span class="comment">/* Populate configuration structure (code specific for CM4) */</span></div><div class="line"><span class="keyword">const</span> <a class="code" href="structcy__stc__sysint__t.html">cy_stc_sysint_t</a> spiIntrConfig =</div><div class="line">{</div><div class="line">    .<a class="code" href="structcy__stc__sysint__t.html#a204a8f07adf056c8d3dd818136da853f">intrSrc</a>      = SPI_INTR_NUM,</div><div class="line">    .intrPriority = SPI_INTR_PRIORITY,</div><div class="line">};</div><div class="line"></div><div class="line"><span class="comment">/* Hook interrupt service routine and enable interrupt */</span></div><div class="line">(void) <a class="code" href="group__group__sysint__functions.html#gab2ff6820a898e9af3f780000054eea5d">Cy_SysInt_Init</a>(&amp;spiIntrConfig, &amp;SPI_Isr);</div><div class="line">NVIC_EnableIRQ(SPI_INTR_NUM);</div><div class="line">}</div></div><!-- fragment --><div class="fragment"><div class="line"><span class="keywordtype">void</span> SPI_EventHandler(uint32_t events)</div><div class="line">{</div><div class="line"><span class="keywordflow">if</span>(<a class="code" href="group__group__scb__spi__macros__callback__events.html#gaabf6c7b9a105e045cee8219a416a3cba">CY_SCB_SPI_TRANSFER_ERR_EVENT</a> == events)</div><div class="line">{</div><div class="line"><span class="comment">/* Handle the error condition */</span></div><div class="line">}</div><div class="line">}</div><div class="line"><span class="keywordtype">void</span> SPI_Reg_Callback(<span class="keywordtype">void</span>)</div><div class="line">{</div><div class="line"><span class="comment">/* Configure the interrupt */</span></div><div class="line">SPI_Cfg_Isr();</div><div class="line"></div><div class="line"><span class="comment">/* Set the slave interrupt mask register bit for SPI_BUS_ERROR field */</span></div><div class="line"><a class="code" href="group__group__scb__common__functions.html#gaeba4fe92683be8638a7596c3ab54359b">Cy_SCB_SetSlaveInterruptMask</a>(SCB1,  <a class="code" href="group__group__scb__common__macros__slave__intr.html#gad3b06f7900eb49c73ca99538a4d110ef">CY_SCB_SLAVE_INTR_SPI_BUS_ERROR</a>);</div><div class="line"></div><div class="line"><span class="comment">/* Register callback for event notification.</span></div><div class="line"><span class="comment">* It is better to do this during initialization before SPI is enabled.</span></div><div class="line"><span class="comment">*/</span></div><div class="line"><a class="code" href="group__group__scb__spi__interrupt__functions.html#ga5594391e0d6a0b020355761826de2e78">Cy_SCB_SPI_RegisterCallback</a>(SCB1, SPI_EventHandler, &amp;spiContext);</div><div class="line">}</div></div><!-- fragment --><h2><a class="anchor" id="group_scb_spi_enable"></a>
Enable SPI</h2>
<p>Finally, enable the SPI operation by calling <a class="el" href="group__group__scb__spi__general__functions.html#ga7e5d7cb17044cdd8ab1543e038bf89a8">Cy_SCB_SPI_Enable</a>. For the slave, this means that SPI device starts responding to the transfers. For the master, it is ready to execute transfers.</p>
<div class="fragment"><div class="line"><span class="comment">/* Enable SPI to operate */</span></div><div class="line"><a class="code" href="group__group__scb__spi__general__functions.html#ga7e5d7cb17044cdd8ab1543e038bf89a8">Cy_SCB_SPI_Enable</a>(SCB1);</div><div class="line"></div><div class="line"><span class="comment">/* Enable global interrupts */</span></div><div class="line">__enable_irq();</div></div><!-- fragment --><h1><a class="anchor" id="group_scb_spi_use_cases"></a>
Common Use Cases</h1>
<p>The SPI API is the same for the master and slave mode operation and is divided into two categories: <a class="el" href="group__group__scb__spi__low__level__functions.html">Low-Level</a> and <a class="el" href="group__group__scb__spi__high__level__functions.html">High-Level</a>. <br />
<em>Do not mix <b>High-Level</b> and <b>Low-Level</b> API because a Low-Level API can adversely affect the operation of a High-Level API.</em></p>
<h2><a class="anchor" id="group_scb_spi_ll"></a>
Low-Level API</h2>
<p>The <a class="el" href="group__group__scb__spi__low__level__functions.html">Low-Level</a> functions allow interacting directly with the hardware and do not use <a class="el" href="group__group__scb__spi__interrupt__functions.html#ga0adeb497479d79c9ecea8169cfaff114">Cy_SCB_SPI_Interrupt</a>. These functions do not require context for operation. Thus, NULL can be passed for context parameter in <a class="el" href="group__group__scb__spi__general__functions.html#gabe68169c810119b93e1164127663033c">Cy_SCB_SPI_Init</a> and <a class="el" href="group__group__scb__spi__general__functions.html#ga01fcd87713fe370d94828563ff1e86b8">Cy_SCB_SPI_Disable</a> instead of a pointer to the context structure.</p>
<ul>
<li>To write data into the TX FIFO, use one of the provided functions: <a class="el" href="group__group__scb__spi__low__level__functions.html#ga6b613c5544c0595763e30d83da125a4d">Cy_SCB_SPI_Write</a>, <a class="el" href="group__group__scb__spi__low__level__functions.html#gad5415bd46d159b57f08fa0eb375a133e">Cy_SCB_SPI_WriteArray</a> or <a class="el" href="group__group__scb__spi__low__level__functions.html#ga6899c2b1dd9f868a7fb625b03a7ee594">Cy_SCB_SPI_WriteArrayBlocking</a>. Note that in the master mode, putting data into the TX FIFO starts a transfer. Due to the nature of SPI, the received data is put into the RX FIFO.</li>
<li>To read data from the RX FIFO, use one of the provided functions: <a class="el" href="group__group__scb__spi__low__level__functions.html#ga169c313a3508261fa76e6b6600cce726">Cy_SCB_SPI_Read</a> or <a class="el" href="group__group__scb__spi__low__level__functions.html#gaecc7c7a8d0ba840fa5d65e5076cb9d84">Cy_SCB_SPI_ReadArray</a>. Again due to the nature of SPI these functions do not start a transfer on the bus, they only read data out of the RX FIFO that has already been received.</li>
<li>The statuses can be polled using: <a class="el" href="group__group__scb__spi__low__level__functions.html#ga50acb3879906a729e5821fcc87d4f017">Cy_SCB_SPI_GetRxFifoStatus</a>, <a class="el" href="group__group__scb__spi__low__level__functions.html#ga987fdbe86c1fbfbadfa51cdf82f84632">Cy_SCB_SPI_GetTxFifoStatus</a> and <a class="el" href="group__group__scb__spi__low__level__functions.html#gac9e9a4b77a8db35ccbda974e7f9d9d23">Cy_SCB_SPI_GetSlaveMasterStatus</a>. <em>The statuses are <b>W1C (Write 1 to Clear)</b> and after a status is set, it must be cleared.</em> Note that there are statuses evaluated as level. These statuses remain set until an event is true. Therefore, after the clear operation, the status is cleared but then it is restored (if the event is still true). Also, the following functions can be used for polling as well <a class="el" href="group__group__scb__spi__general__functions.html#ga4241f6166816159f7365220834a5e0d0">Cy_SCB_SPI_IsBusBusy</a>, <a class="el" href="group__group__scb__spi__low__level__functions.html#ga399842a2931b7c6cd85446a72cc2f81b">Cy_SCB_SPI_IsTxComplete</a>, <a class="el" href="group__group__scb__spi__low__level__functions.html#gaea6c37058e015b59c0e307d0d0e77ad0">Cy_SCB_SPI_GetNumInRxFifo</a> and <a class="el" href="group__group__scb__spi__low__level__functions.html#gad9be16f0ae646a85e9fffe9731cb4896">Cy_SCB_SPI_GetNumInTxFifo</a>.</li>
</ul>
<div class="fragment"><div class="line">uint8_t txBuffer[BUFFER_SIZE];</div><div class="line"></div><div class="line"><span class="comment">/* Initialize txBuffer with command to transfer */</span></div><div class="line">txBuffer[0] = CMD_START_TRANSFER;</div><div class="line">txBuffer[1] = 0x00U;</div><div class="line">txBuffer[2] = 0x01U;</div><div class="line"></div><div class="line"><span class="comment">/* Master: start a transfer. Slave: prepare for a transfer. */</span></div><div class="line"><a class="code" href="group__group__scb__spi__low__level__functions.html#ga6899c2b1dd9f868a7fb625b03a7ee594">Cy_SCB_SPI_WriteArrayBlocking</a>(SCB1, txBuffer, <span class="keyword">sizeof</span>(txBuffer));</div><div class="line"></div><div class="line"><span class="comment">/* Blocking wait for transfer completion */</span></div><div class="line"><span class="keywordflow">while</span> (!<a class="code" href="group__group__scb__spi__low__level__functions.html#ga399842a2931b7c6cd85446a72cc2f81b">Cy_SCB_SPI_IsTxComplete</a>(SCB1))</div><div class="line">{</div><div class="line">}</div><div class="line"></div><div class="line"><span class="comment">/* Handle results of a transfer */</span></div></div><!-- fragment --><h2><a class="anchor" id="group_scb_spi_hl"></a>
High-Level API</h2>
<p>The <a class="el" href="group__group__scb__spi__high__level__functions.html">High-Level</a> API use <a class="el" href="group__group__scb__spi__interrupt__functions.html#ga0adeb497479d79c9ecea8169cfaff114">Cy_SCB_SPI_Interrupt</a> to execute the transfer. Call <a class="el" href="group__group__scb__spi__high__level__functions.html#ga6fdbb98ef7faddc5025fab510fb1617e">Cy_SCB_SPI_Transfer</a> to start communication: for master mode calling this function starts a transaction with the slave. For slave mode the read and write buffers are prepared for the communication with the master. After a transfer is started, the <a class="el" href="group__group__scb__spi__interrupt__functions.html#ga0adeb497479d79c9ecea8169cfaff114">Cy_SCB_SPI_Interrupt</a> handles the transfer until its completion. Therefore, the <a class="el" href="group__group__scb__spi__interrupt__functions.html#ga0adeb497479d79c9ecea8169cfaff114">Cy_SCB_SPI_Interrupt</a> function must be called inside the user interrupt handler to make the High-Level API work. To monitor the status of the transfer operation, use <a class="el" href="group__group__scb__spi__high__level__functions.html#ga95069817e25be749ae989e5d7131f8d0">Cy_SCB_SPI_GetTransferStatus</a>. Alternatively, use <a class="el" href="group__group__scb__spi__interrupt__functions.html#ga5594391e0d6a0b020355761826de2e78">Cy_SCB_SPI_RegisterCallback</a> to register a callback function to be notified about <a class="el" href="group__group__scb__spi__macros__callback__events.html">SPI Callback Events</a>.</p>
<div class="fragment"><div class="line">uint8_t rxBuffer[BUFFER_SIZE];</div><div class="line">uint8_t txBuffer[BUFFER_SIZE];</div><div class="line"></div><div class="line"><span class="comment">/* Initialize txBuffer with command to transfer */</span></div><div class="line">txBuffer[0] = CMD_START_TRANSFER;</div><div class="line">txBuffer[1] = 0x00U;</div><div class="line">txBuffer[2] = 0x01U;</div><div class="line"></div><div class="line"><span class="comment">/* Master: start a transfer. Slave: prepare for a transfer. */</span></div><div class="line">(void) <a class="code" href="group__group__scb__spi__high__level__functions.html#ga6fdbb98ef7faddc5025fab510fb1617e">Cy_SCB_SPI_Transfer</a>(SCB1, txBuffer, rxBuffer, <span class="keyword">sizeof</span>(txBuffer), &amp;spiContext);</div><div class="line"></div><div class="line"><span class="comment">/* Blocking wait for transfer completion */</span></div><div class="line"><span class="keywordflow">while</span> (0UL != (<a class="code" href="group__group__scb__spi__macros__xfer__status.html#gab024f7d6ed7cbaa36c80c904a6179de7">CY_SCB_SPI_TRANSFER_ACTIVE</a> &amp; <a class="code" href="group__group__scb__spi__high__level__functions.html#ga95069817e25be749ae989e5d7131f8d0">Cy_SCB_SPI_GetTransferStatus</a>(SCB1, &amp;spiContext)))</div><div class="line">{</div><div class="line">}</div><div class="line"></div><div class="line"><span class="comment">/* Handle results of a transfer */</span></div></div><!-- fragment --><h1><a class="anchor" id="group_scb_spi_dma_trig"></a>
DMA Trigger</h1>
<p>The SCB provides TX and RX output trigger signals that can be routed to the DMA controller inputs. These signals are assigned based on the data availability in the TX and RX FIFOs appropriately.</p>
<ul>
<li>The RX trigger signal is active while the number of data elements in the RX FIFO is greater than the value of RX FIFO level. Use function <a class="el" href="group__group__scb__common__functions.html#ga64d034531ea5eb2695ed018d6a75da68">Cy_SCB_SetRxFifoLevel</a> or set configuration structure rxFifoTriggerLevel parameter to configure RX FIFO level value. <br />
 <em>For example, the RX FIFO has 8 data elements and the RX FIFO level is 0. The RX trigger signal is active until DMA reads all data from the RX FIFO.</em></li>
<li>The TX trigger signal is active while the number of data elements in the TX FIFO is less than the value of TX FIFO level. Use function <a class="el" href="group__group__scb__common__functions.html#ga36285e337c94df91a4ebe5b1ee0fd43d">Cy_SCB_SetTxFifoLevel</a> or set configuration structure txFifoTriggerLevel parameter to configure TX FIFO level value. <br />
 <em>For example, the TX FIFO has 0 data elements (empty) and the TX FIFO level is 7. The TX trigger signal is active until DMA loads TX FIFO with 8 data elements (note that after the first TX load operation, the data element goes to the shift register and TX FIFO is empty).</em></li>
</ul>
<p>To route SCB TX or RX trigger signals to the DMA controller, use <a class="el" href="group__group__trigmux.html">TrigMux (Trigger Multiplexer)</a> driver API.</p>
<dl class="section note"><dt>Note</dt><dd>To properly handle DMA level request signal activation and de-activation from the SCB peripheral block the DMA Descriptor typically must be configured to re-trigger after 16 Clk_Slow cycles.</dd></dl>
<h1><a class="anchor" id="group_scb_spi_lp"></a>
Low Power Support</h1>
<p>The SPI driver provides callback functions to handle power mode transitions. The callback <a class="el" href="group__group__scb__spi__low__power__functions.html#gabf413c42a9ba8a20c38f2491ae2e36c0">Cy_SCB_SPI_DeepSleepCallback</a> must be called during execution of <a class="el" href="group__group__syspm__functions__power.html#ga5150c28fe4d2626720c1fbf74b3111ca">Cy_SysPm_CpuEnterDeepSleep</a>; <a class="el" href="group__group__scb__spi__low__power__functions.html#ga1bf16639bec6ac8209621227bd5ac0e3">Cy_SCB_SPI_HibernateCallback</a> must be called during execution of <a class="el" href="group__group__syspm__functions__power.html#gae97647a28c370674ba57d451d21d1c51">Cy_SysPm_SystemEnterHibernate</a>. To trigger the callback execution, the callback must be registered before calling the power mode transition function. Refer to <a class="el" href="group__group__syspm.html">SysPm (System Power Management)</a> driver for more information about power mode transitions and callback registration.</p>
<p>The SPI master is disabled during Deep Sleep and Hibernate and stops driving the output pins. The state of the SPI master output pins SCLK, SS, and MOSI is High-Z, which can cause unexpected behavior of the SPI Slave due to possible glitches on these lines. These pins must keep the inactive level (the same state when SPI master is enabled and does not transfer data) before entering Deep Sleep or Hibernate mode. To do that, write the GPIO data register of each pin to the inactive level for each output pin. Then configure High-Speed Input Output Multiplexer (HSIOM) of each pin to be controlled by the GPIO (use <a class="el" href="group__group__gpio.html">GPIO (General Purpose Input Output)</a> driver API). After after exiting Deep Sleep mode the SPI master must be enabled and the pins configuration restored to return the SPI master control of the pins (after exiting Hibernate mode, the system initialization code does the same). Copy either or both <a class="el" href="group__group__scb__spi__low__power__functions.html#gabf413c42a9ba8a20c38f2491ae2e36c0">Cy_SCB_SPI_DeepSleepCallback</a> and <a class="el" href="group__group__scb__spi__low__power__functions.html#ga1bf16639bec6ac8209621227bd5ac0e3">Cy_SCB_SPI_HibernateCallback</a> as appropriate, and make the changes described above inside the function. Alternately, external pull-up or pull-down resistors can be connected to the appropriate SPI lines to keep them inactive during Deep-Sleep or Hibernate.</p>
<dl class="section note"><dt>Note</dt><dd>Only applicable for <b>rev-08 of the CY8CKIT-062-BLE</b>. For proper operation, when the SPI slave is configured to be a wakeup source from Deep Sleep mode, the <a class="el" href="group__group__scb__spi__low__power__functions.html#gabf413c42a9ba8a20c38f2491ae2e36c0">Cy_SCB_SPI_DeepSleepCallback</a> must be copied and modified. Refer to the function description to get the details. </dd></dl>
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